If you wanna make your own open-source chip, just Google it. Literally. Web giant says it’ll fab them for free

If you’re doodling your own computer chip yet wondering if you’ll ever see it physically manufactured, Google is offering to fabricate it for you for free.

There are a few caveats.

One is that the chip design must be public and open-source: you’ll submit your work by sending in a URL to the relevant Git repo. The other is that the process node will be 130nm, which was cutting edge circa 2001. Another is that while Google has promised to fab any open-source project – whether it’s an academic or amateur effort, or led by a commercial outfit – if more than 40 groups step forward for free gear, it’ll start selecting which ones to accept into the program. Also, you’ll each get about 100 components off the production line. And your die area is 10mm2.

But hey, it’s free – and seeing as the step from writing and verifying a chip in a hardware language and simulator to actually getting it fabbed is quite large and daunting for most people, the offer isn’t bad. It typically costs thousands of dollars to prototype chips using even that modest process node.

More details are here, and you can watch the video below to get it all direct from the person spearheading the program, veteran Google software engineer Tim Ansell.

Youtube Video

As for who will actually make the chips, Google, and its partner efabless, chose SkyWater Technology Foundry, which was spun out of Cypress Semiconductor. A production run is scheduled for November this year, and another in early 2021, and more after.

The goal is to develop an entirely open-source semiconductor manufacturing workflow. To help achieve this, Google and Skywater released an open-source PDK, or process development kit, which is described as a grab bag of design rules, logic and analog models and cells, specifications, and other data to turn your RTL files into actual working patterns of semiconductors, metals, and other chemicals on tiny squares of plastic-packaged silicon.

Normally, PDKs from foundries involve a lot of money; this one is free – the first-ever open source one, apparently – though it is a work-in-progress experiment.

And if you’re worried about Google using this as a means to snaffle your intellectual property, don’t forget: it’s only for public projects that are open-source all the way down to the silicon layout. So if you qualify, you’ve already handed over your work to the world anyway.

PS: If anyone wants to collaborate on designing an open-source chip and pitch it at Google-Skywater, let us know. We’ve been pondering drawing up a basic AI math chip as a Special Project.

Berkeley SonicBOOM ‘fastest’ open-source RISC-V

A team at University of California, Berkeley in the US say they have produced the world’s fastest open-source RISC-V CPU by IPC – that’s instructions per clock cycle.

This third-generation design is dubbed SonicBOOM; the BOOM stands for Berkeley Out of Order Machine because, well, it is. It’s a superscalar out-of-order 64-bit RISC-V (RV64GC) core with 32KB of L1 instruction cache and 32KB of L1 data cache, and 512KB of L2 cache.

Its performance is said to reach 3.93 DMIPS/MHz, or 6.2 CoreMark/MHz, putting on a par with early Intel Core Duo parts circa 2006. That’s not bad for a work-in-progress, completely free and open-source academic project that you can leaf through. If you want to see what non-trivial branch prediction, cache management, instruction decoding and scheduling, and out-of-order execution look like under the hood, it’s all there for you.

Well, provided any contract you’re under allows you to look at this sort of stuff in open-source projects.

SonicBOOM is synthesizable and parameterizable, written in the hardware design language Chisel, and boots Linux. You can find the royalty-free code for it here, and a paper describing its design here [PDF]. An 18-minute video outlining its operation and features is here.

You can spin it up in a suitable FPGA, or turn it into a proper system-on-chip design with math accelerators and IO and other stuff bolted on via Berkeley’s Chipyard tooling.

IBM opens up supercomputer processor core

IBM has released the VHDL source code for its A2I POWER processor core, used in its BlueGene/Q supercomputers from the early 2010s, along with materials needed to spin it up in an FPGA.

Like with the SonicBOOM, it’s an opportunity to peek under the hood and see what a production-grade processor looks like, if you can stomach reams of VHDL. The A2I was developed as a general-purpose 45nm CPU for supercomputers and, prior to that, as an edge-of-network processor core operating at wire speed. It supports big- and little-endian modes.

The A2I is a four-way SMT, two-way issue CPU design that executes 64-bit POWER v2.06 Book III-E code in-order with dynamic branch prediction. It has 16KB of L1 data and 16KB of L1 instruction cache. Typically, multiple cores were packaged per processor chip; 18 for the BlueGene/Q clocked at 1.6GHz, for instance.

Our sister site The Next Platform has more history and analysis here, and notes that Big Blue has opened up the central A2I core not the full processor – so things like the floating-point math engines that made it supercomputer-grade appear to be missing.

The A2I blueprints are available under a Creative Commons license that lets you use and adapt the core design as you wish provided you credit Big Blue. You can use it in a physical chip at no cost if you speak to the OpenPOWER Foundation about a license. ®

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